Instruction Encoding

The questions below are due on Sunday October 25, 2026; 11:59:00 PM.

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RISC-V Instruction Encoding

The following questions ask you to provide the 32-bit binary encoding of different RISC-V instructions. You will need to use the RISC-V ISA handout for reference. For clarity, please separate each field of the instruction with an underscore in your answer (e.g., 11111_00000).

What is the 32-bit binary encoding of the instruction xor x2, x4, x6? 0b

What is the 32-bit binary encoding of the instruction slti x3, x3, 7? 0b

What is the 32-bit binary encoding of the instruction srai x7, x8, 24? 0b

What is the 32-bit binary encoding of the instruction bge x2, x3, label if label is 4 instructions after the current instruction (pay close attention to how the branch offset gets encoded)? 0b

What is the 32-bit binary encoding of the instruction sw x6, 8(x2)? 0b

Consider the 32-bit binary value 0b0000000_00000_00001_110_00101_0010011. If you interpret this number as a 2's complement number what value does it represent? You can express your answer as a python expression that sums powers of 2 (e.g., 2**3 + 2**5).

Consider the 32-bit binary value 0b0000000_00000_00001_110_00101_0010011. If you interpret this number as the encoding of a risc-v instruction, which instruction does this encoding translate into?

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