Recitation 4

The questions below are due on Tuesday October 20, 2026; 11:59:00 PM.
 
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1) Translating C to Assembly

Complete the translation of each expression to RISC-V assembly.

For problem 1, assume:

  • a is stored at address 0x1000.
  • b is stored at address 0x1004.
  • c is stored at address 0x1008.
  • All values are 32-bit signed integers.

1.1) Loading and Adding

Expression:

    a = b + 3*c

RISC-V assembly:

Only use registers x0 and registers greater than or equal to x5.

1.2) Branching

Expression:

    if (a > b) {
        c = 17;
    }

RISC-V assembly:

1.3) Looping

Expression:

    int sum = 0;
    for (int i = 0; i < 10; i++){
        sum += i;
    }

RISC-V assembly:

2) More Translating

Complete the translation of the following expression to RISC-V assembly.

For this problem, assume:

  • a is stored at address 0x1100.
  • b is stored at address 0x1200.
  • c is stored at address 0x2000.
  • a, b, and c are arrays whose elements are stored in consecutive memory locations.
  • All values are 32-bit signed integers.

In the questions below, enter address offsets in hexadecimal (e.g., 0x4).

Expression:

    for (int i = 0; i < 10; i++) {
        c[i] = a[i] + b[i];
    }

RISC-V assembly:

3) Instructions are Bits!

Assemble the following instruction into its equivalent binary encoding.

Hint: use the ISA Reference Card to parse and encode the instruction.

Instruction:

    addi x1, x1, -1

What is the 32 bit binary encoding of the addi x1, x1, -1 instruction? For clarity, please separate each field of the instruction with an underscore (e.g., 11111_00000). 0b

    slti x1, x3, -79

(optional)

What is the 32 bit binary encoding of the slti x1, x3, -79 instruction? For clarity, please separate each field of the instruction with an underscore (e.g., 11111_00000). 0b

Bits:

0x12341234: 0b0000_0000_0111_0001_0101_1000_0110_0011

We are about to execute the instruction at address 0x12341234. It's a branching instruction with a 32 bit binary encoding as shown above.

(optional)

If the branching condition is met, what is the address of the instruction that will be executed next? 0x

4) Working with Registers

4.1) Part 1 (optional)

For this part, assume that the registers are initialized to the following before the execution of any assembly instructions:

  • a1 = 8
  • a2 = 10
  • a3 = 12
  • a4 = 0x1234
  • a5 = 24

For each of the following instructions, provide the value of the specified register or memory location.

Instruction 1:

    sll a6, a4, a5

Value of a6 in hexadecimal: 0x

Instruction 2:

    add a7, a3, a2

Value of a7 in decimal:

Instruction 3:

    addi t0, a1, 2

Value of t0 in decimal:

Instruction 4:

    sw a2, 4(a4)

Value stored in memory:

Memory address being written to in 32-bit hexadecimal: 0x

4.2) Part 2 (optional)

In the following set of instructions, assume X is at address 0x23E8.

    lui a1, 0x2
    addi a1, a1, 0x3E8
    lw a4, 0(a1)
    blt a4, x0, L1
    addi a2, a0, 17
    beq x0, x0, L2
L1: srai a2, a4, 4
L2:

X: .word 0x87654321

Value left in a4 in 32-bit hexadecimal: 0x

Value left in a2 in 32-bit hexadecimal: 0x

5) (optional) Fibonassembly

Translate the following Fibonacci implementation to RISC-V assembly.

# Reference Fibonacci implementation in Python
def fibonacci_iterative(n:int) -> int:
    """Obtain the nth Fibonacci number."""
    if n == 0:
        return 0
    n = n-1
    # Parallel assignment of x and y
    x, y = 0, 1
    while n > 0:
        # The new values for x and y are computed at the same time
        # and then the values of x and y are updated afterwards
        x, y = y, x+y
        n = n-1
    return y

RISC-V assembly:

6) Bug Hunt

Let's explore how to use a debugger to investigate assembly code! The assembly tutor includes debugging features accessible using a special keyword, csbreak.

See the debugger reference for documentation of the provided features.

6.1) Summing an Array (optional)

C Code:

    int sum = 0;
    for (int i = 0; i < n; i++) {
        sum += arr[i];
    }

RISC-V assembly:

In the following code, assume the starting address of arr is in register a5, and n is in register a1. The result will be stored in a0 (a0 is an alias for x10).

First, run the program and view its result. The provided implementation will pass the test case.

Value in a0: 0x

Now, insert a csbreak keyword after line 5. Submit your program to enter debug mode. Open the debugger and the embedded register view. Then, press continue to start running your program. The debugger will pause execution when csbreak is reached.

Value of n: 0x

Which register is uesd to represent the address of arr[i]?

6.2) Undefined Behavior (optional)

The provided test input is slightly problematic... Monitor the partial sums stored in a0. The sum of this array of integers cannot be represented using 32 bits. Now, determine which index i causes sum += arr[i] to overflow.

Value of i in decimal:

The C programming language defines overflow behavior for unsigned integers, but overflow of signed integers is an example of undefined behavior. This means that results of running this C program will vary depending on the underlying instruction set architecture. Fortunately, signed integer overflow is well defined by a given RISC-V implementation (it may be handled differently). Is this a 'bug' or a 'feature'...? In an extreme case, this undefined behavior can cause the program to crash.